@inproceedings {INPROC-2002-47,
   author = {Arnaud Virazel and Hans-Joachim Wunderlich},
   title = {{Power Conscious BIST Approaches}},
   booktitle = {3. VIVA Schwerpunkt-Kolloquium; Chemnitz, Germany; 18. - 19. March 2002},
   publisher = {-},
   institution = {University of Stuttgart, Faculty of Computer Science, Germany},
   pages = {128--135},
   type = {Conference Paper},
   month = {March},
   year = {2002},
   isbn = {3-00-008 995-0},
   language = {English},
   cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
   department = {University of Stuttgart, Institute of Computer Science, Computer Architecture},
   abstract = {The System-On-Chip (SOC) revolution has brought some new challenges to both
      design and test engineers. The most important challenges of today’s VLSI
      systems testing are linked to test cost, defect coverage and power dissipation.
      Implementing a self-testable system may reduce test costs as expensive external
      high performance test equipment is not required and it may increase defect
      coverage as testing is performed at system speed. Unfortunately, the classic
      BIST approaches lead to a significant increase of power consumption compared to
      the system mode and even compared to external testing. The paper will review
      required changes to be applied to classic BIST techniques for power reduction.
      A recently developed new BIST approach called functional BIST is introduced and
      its consequences for power dissipation are discussed.},
   url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2002-47&engl=1}
}

@inproceedings {INPROC-2002-45,
   author = {Lars Schaefer and Rainer Dorsch and Hans-Joachim Wunderlich},
   title = {{RESPIN++ - Deterministic Embedded Test}},
   booktitle = {Proceedings of the 7th European Test Workshop (ETW), Korfu, Greece, May 26-29, 2002},
   publisher = {Institute of Electrical and Electronics Engineers},
   institution = {University of Stuttgart, Faculty of Computer Science, Germany},
   pages = {139--146},
   type = {Conference Paper},
   month = {May},
   year = {2002},
   isbn = {0-7695-1715-3},
   issn = {1530-1877},
   doi = {10.1109/ETW.2002.1029637},
   language = {English},
   cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
   department = {University of Stuttgart, Institute of Computer Science, Computer Architecture},
   abstract = {RESPIN++ is a deterministic embedded test method tailored to system chips,
      which implement scan test at core level. The scan chains of one core of the
      system-on-a-chip are reused to decompress the patterns for another core. To
      implement the RESPIN++ test architecture only a few gates need to be added to
      the test wrapper. This will not affect the critical paths of the system. The
      RESPIN++ method reduces both test data volume and test application time up to
      one order of magnitude per core compared to storing compacted test patterns on
      the ATE. If several cores may be tested concurrently, test data volume and test
      application time for the complete system test may be reduced even further. This
      paper presents the RESPIN++ test architecture and a compression algorithm for
      the architecture.},
   url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2002-45&engl=1}
}

@inproceedings {INPROC-2002-44,
   author = {Harald Vranken and Florian Meister and Hans-Joachim Wunderlich},
   title = {{Combining Deterministic Logic BIST with Test Point Insertion}},
   booktitle = {Proceedings of the 7th European Test Workshop (ETW'02); Korfu, Greece; May 26-29, 2002},
   editor = {IEEE Computer Society},
   address = {Los Alamitos, California},
   publisher = {IEEE Computer Society},
   institution = {University of Stuttgart, Faculty of Computer Science, Germany},
   series = {IEEE Computer Society Order Number},
   volume = {PR01715},
   pages = {105--110},
   type = {Conference Paper},
   month = {May},
   year = {2002},
   isbn = {0-7695-1715-3},
   issn = {1530-1877},
   doi = {10.1109/ETW.2002.1029646},
   language = {English},
   cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
   department = {University of Stuttgart, Institute of Computer Science, Computer Architecture},
   abstract = {This paper presents a logic BIST approach which combines deterministic logic
      BIST with test point insertion. Test points are inserted to obtain a first
      testability improvement, and next a deterministic pattern generator is added to
      increase the fault efficiency up to 100\%. The silicon cell area for the
      combined approach is smaller than for approaches that apply a deterministic
      pattern generator or test points only. The combined approach also removes the
      classical limitations and drawbacks of test point insertion, such as failing to
      achieve complete fault coverage and a complicated design flow. The benefits of
      the combined approach are demonstrated in experimental results on a large
      number of ISCAS and industrial circuits.},
   url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2002-44&engl=1}
}

@inproceedings {INPROC-2002-43,
   author = {Rainer Dorsch and Ram{\'o}n Huerta Rivera and Hans-Joachim Wunderlich and Martin Fischer},
   title = {{Adapting a SoC to ATE Concurrent Test Capabilities}},
   booktitle = {Proceedings of the 33rd International Test Conference (ITC), Baltimore, MD, October 8-10, 2002},
   publisher = {International Test Conference},
   institution = {University of Stuttgart, Faculty of Computer Science, Electrical Engineering, and Information Technology, Germany},
   pages = {1169--1175},
   type = {Conference Paper},
   month = {October},
   year = {2002},
   isbn = {0-7803-7542-4},
   isbn = {ISSN 1089-3539},
   doi = {10.1109/TEST.2002.1041875},
   keywords = {ATE; concurrent test; SoC test; test resource partitioning},
   language = {English},
   cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
   department = {University of Stuttgart, Institute of Technical Computer Science, Computer Architecture},
   abstract = {Concurrent test features are available in the next generation SoC testers to
      increase ATE throughput. To exploit these new features design modifications are
      necessary. In a case study, these modifications were applied to the open source
      Leon SoC platform containing an embedded 32 bit CPU, an AMBA bus, and several
      embedded cores. The concurrent test of Leon was performed on an SoC tester. The
      gain in test application time and area costs are quantified and obstacles in
      the design flow for concurrent test are discussed.},
   url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2002-43&engl=1}
}

@article {ART-2002-14,
   author = {Rainer Dorsch and Hans-Joachim Wunderlich},
   title = {{Reusing Scan Chains for Test Pattern Decompression}},
   journal = {Journal of Electronic Testing - Theory and Applications (JETTA)},
   publisher = {Springer Netherlands},
   volume = {18},
   number = {2},
   pages = {231--240},
   type = {Article in Journal},
   month = {April},
   year = {2002},
   isbn = {0923-8174},
   doi = {10.1023/A:1014968930415},
   keywords = {system-on-a-chip; embedded test; BIST},
   language = {English},
   cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
   department = {University of Stuttgart, Institute of Computer Science, Computer Architecture},
   abstract = {The paper presents a method for testing a system-on-a-chip by using a
      compressed representation of the patterns on an external tester. The patterns
      for a certain core under test are decompressed by reusing scan chains of cores
      idle during that time. The method only requires a few additional gates in the
      wrapper, while the mission logic is untouched. Storage and bandwidth
      requirements for the ATE are reduced significantly.},
   url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-2002-14&engl=1}
}

@article {ART-2002-11,
   author = {Hua-Guo Liang and Sybille Hellebrand and Hans-Joachim Wunderlich},
   title = {{Two-Dimensional Test Data Compression for Scan-Based Deterministic BIST}},
   journal = {Journal of Electronic Testing - Theory and Applications (JETTA)},
   publisher = {Springer Netherlands},
   volume = {18},
   number = {2},
   pages = {157--168},
   type = {Article in Journal},
   month = {April},
   year = {2002},
   issn = {0923-8174},
   doi = {10.1023/A:1014993509806},
   keywords = {BIST; deterministic BIST; store and generate schemes; test data compression},
   language = {English},
   cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
   department = {University of Stuttgart, Institute of Computer Science, Computer Architecture},
   abstract = {In this paper a novel architecture for scan-based mixed mode BIST is presented.
      To reduce the storage requirements for the deterministic patterns it relies on
      a two-dimensional compression scheme, which combines the advantages of known
      vertical and hoizontal compression techniques. To reduce both the number of
      patterns to be stored and the number of bits to be stored for each pattern,
      deterministic test cubes are encoded as seeds of an LFSR (horizontal
      compression), and the seeds are again compressed into seeds of a folding
      counter sequence (vertical compression). The proposed BIST architecture is
      fully compatible with standard scan esign, simple and flexible, so that sharing
      between several logic cores is p0ossible. Experimental results show that the
      proposed scheme requires less test data storage than previously publiched
      approaches providing the same flexibility and scan compatibility.},
   url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-2002-11&engl=1}
}

@article {ART-2002-10,
   author = {Sybille Hellebrand and Hans-Joachim Wunderlich and Alexander A. Ivaniuk and Yuri V. Klimets and Vyacheslav N. Yarmolik},
   title = {{Efficient On- and Off-Line Testing of Embedded DRAMs}},
   journal = {IEEE Transaction on Computers},
   publisher = {IEEE Computer Society},
   volume = {51},
   number = {7},
   pages = {801--809},
   type = {Article in Journal},
   month = {July},
   year = {2002},
   issn = {0018-9340},
   doi = {10.1109/TC.2002.1017700},
   keywords = {Embedded memories; systems-on-a-chip; online checking; BIST},
   language = {English},
   cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
   department = {University of Stuttgart, Institute of Computer Science, Computer Architecture},
   abstract = {This paper presents an integrated approach for both built-in online and offline
      testing of embedded DRAMs. It is based on a new technique for output data
      compression which offers the same benefits as signature analysis during offline
      test, but also supports efficient online consistency checking. The initial
      fault-free memory contents are compressed to a reference characteristic and
      compared to test characteristics periodically. The reference characteristic
      depends on the memory contents, but unlike similar characteristics based on
      signature analysis, it can be easily updated concurrently with WRITE
      operations. This way, changes in memory do not require a time consuming
      recomputation. The respective test characteristics can be efficiently computed
      during the periodic refresh operations of the dynamic RAM. Experiments show
      that the proposed technique significantly reduces the time between the
      occurrence of an error and its detection (error detection latency). Compared to
      error detecting codes (EDC) it also achieves a significantly higher error
      coverage at lower hardware costs. Therefore, it perfectly complements standard
      online checking approaches relying on EDC, where the concurrent detection of
      certain types of errors is guaranteed, but only during READ operations
      accessing the erroneous data.},
   url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-2002-10&engl=1}
}

@article {ART-2002-09,
   author = {Patrick Girard and Christian Landrault and Serge Pravossoudovitch and Arnaud Virazel and Hans-Joachim Wunderlich},
   title = {{High Defect Coverage with Low Power Test Sequences in a BIST Environment}},
   journal = {IEEE Design and Test of Computers},
   publisher = {IEEE Computer Society},
   volume = {19},
   number = {5},
   pages = {44--52},
   type = {Article in Journal},
   month = {September},
   year = {2002},
   issn = {0740-7475},
   doi = {10.1109/MDT.2002.1033791},
   language = {English},
   cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
   department = {University of Stuttgart, Institute of Computer Science, Computer Architecture},
   abstract = {A new technique, random single-input change (RSIC) test generation, generates
      low-power test patterns that provide a high level of defect coverage during
      low-power BIST of digital circuits. The authors propose a parallel BIST
      implementation of the RSIC generator and analyze its area-overhead impact.},
   url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-2002-09&engl=1}
}