@inproceedings {INPROC-2005-128,
   author = {Jun Zhou and Hans-Joachim Wunderlich},
   title = {{Software-basierender Selbsttest von Prozessorkernen unter Verlustleistungsbeschr{\"a}nkung}},
   booktitle = {INFORMATIK 2005 - Informatik LIVE! Band 1, Beitr{\"a}ge der 35. Jahrestagung der Gesellschaft f{\"u}r Informatik e.V. (GI), Bonn, 19. bis 22. September 2005},
   editor = {Armin B. Cremers and Rainer Manthey and Peter Martini and Volker Steinhage},
   address = {Bonn},
   publisher = {K{\"o}llen Druck+Verlag GmbH},
   institution = {University of Stuttgart, Faculty of Computer Science, Electrical Engineering, and Information Technology, Germany},
   series = {Lecture Notes in Informatics},
   volume = {P-67},
   pages = {441--441},
   type = {Conference Paper},
   month = {September},
   year = {2005},
   isbn = {3-88579-396-2},
   issn = {1617-5468},
   language = {German},
   cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
   department = {University of Stuttgart, Institute of Technical Computer Science, Computer Architecture},
   abstract = {},
   url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2005-128&engl=1}
}

@inproceedings {INPROC-2005-118,
   author = {Patrick Jaeger and Bernd Bertsche and Talal Arnout and Hans-Joachim Wunderlich},
   title = {{Fr{\"u}he Zuverl{\"a}ssigkeitsanalyse mechatronischer Systeme}},
   booktitle = {VDI Berichte 1884, 22. VDI Tagung Technische Zuverl{\"a}ssigkeit (TTZ'05); Stuttgart; April 7-8, 2005},
   address = {D{\"u}sseldorf},
   publisher = {VDI Verlag},
   institution = {University of Stuttgart, Faculty of Computer Science, Electrical Engineering, and Information Technology, Germany},
   pages = {39--56},
   type = {Conference Paper},
   month = {April},
   year = {2005},
   language = {German},
   cr-category = {A General Literature},
   department = {University of Stuttgart, Institute of Technical Computer Science, Computer Architecture},
   abstract = {Mechatronische Systeme sind heutzutage allgegenw{\"a}rtig. Durch die Kombination
      aus Mechanik und moderner Informationsverarbeitung (Elektronik und Software)
      kann die Leistungsf{\"a}higkeit von Produkten deutlich gesteigert werden. Ein
      Beispiel hierf{\"u}r sind CVTGetriebe. Die ersten Getriebe dieser Bauart waren
      weitgehend mechanisch/hydraulische Strukturen [1]. Modernere CVT-Getriebe, wie
      das ZF Ecotronic [2] oder das Front-CVT der Mercedes-Benz A-Klasse [3] verf{\"u}gen
      {\"u}ber eine elektronische Steuerung, die die Leistungsf{\"a}higkeit des Getriebes zu
      steigern vermag aber auch zu UnZuverl{\"a}ssigkeiten f{\"u}hren kann. In diesem Beitrag
      soll das Thema der Zuverl{\"a}ssigkeit mechatronischer Systeme aufgegriffen werden
      und insbesondere vor dem Hintergrund der Zuverl{\"a}ssigkeitsarbeit in Fr{\"u}hen
      Entwicklungsphasen diskutiert werden, da namentlich die Konzeptphase durch die
      Auswahl des richtigen Konzeptes f{\"u}r den endg{\"u}ltigen Produkterfolg
      hauptverantwortlich ist. Hierzu wird speziell das Thema der
      Informationsgewinnung in Fr{\"u}hen Phasen thematisiert, da der Erfolg der
      Zuverl{\"a}ssigkeitsarbeit ma{\ss}geblich von der Daten- und Informationslage abh{\"a}ngig
      ist.},
   url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2005-118&engl=1}
}

@inproceedings {INPROC-2005-117,
   author = {Abdul Wahid Hakmi and Hans-Joachim Wunderlich and Valentin Gherman and Michael Garbers and Juergen Schloeffel},
   title = {{Implementing a Scheme for External Deterministic Self-Test}},
   booktitle = {Proceedings of the 23rd IEEE VLSI Test Sypmposium (VTS'05); Palm Springs, CA, USA; May 1-5, 2005},
   editor = {IEEE Computer Society},
   address = {Los Alamitos, California},
   publisher = {IEEE Computer Society Conference Publishing Services},
   institution = {University of Stuttgart, Faculty of Computer Science, Electrical Engineering, and Information Technology, Germany},
   series = {IEEE Computer Society Order Number},
   volume = {P2314},
   pages = {101--106},
   type = {Conference Paper},
   month = {May},
   year = {2005},
   isbn = {0-7695-2314-5},
   issn = {1093-0167},
   doi = {10.1109/VTS.2005.50},
   keywords = {deterministic self-test; external BIST; test resource partitioning; test data compression},
   language = {English},
   cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
   department = {University of Stuttgart, Institute of Technical Computer Science, Computer Architecture},
   abstract = {A method for test resource partitioning is introduced which keeps the
      design-for-test logic test set independent and moves the test pattern dependent
      information to an external, programmable chip. The scheme includes a new
      decompression scheme for a fast and efficient communication between the
      external test chip and the circuit under test. The hardware costs on chip are
      significantly lower compared with a deterministic BIST scheme while the test
      application time is still in the same range. The proposed scheme is fully
      programmable, flexible and can be reused at board level for testing in the
      field. Keywords: Deterministic self-test, external BIST, test resource
      partitioning, test data compression.},
   url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2005-117&engl=1}
}

@inproceedings {INPROC-2005-116,
   author = {Piet Engelke and Valentin Gherman and Ilia Polian and Yuyi Tang and Hans-Joachim Wunderlich and Bernd Becker},
   title = {{Sequence Length, Area Cost and Non-Target Defect Coverage Tradeoffs in Deterministic Logic BIST}},
   booktitle = {Proceedings of the 8th IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS); Sopron, Hungary; April 13-16, 2005},
   publisher = {Institute of Electrical and Electronics Engineers, Inc.},
   institution = {University of Stuttgart, Faculty of Computer Science, Electrical Engineering, and Information Technology, Germany},
   pages = {11--18},
   type = {Conference Paper},
   month = {April},
   year = {2005},
   keywords = {Test Tradeoffs; Logic BIST; Defect Coverage; Resistive Bridging Faults},
   language = {English},
   cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
   department = {University of Stuttgart, Institute of Technical Computer Science, Computer Architecture},
   abstract = {For the first time, we study the coverage of non-target defects for
      Deterministic Logic BIST (DLBIST) architecture. We consider several DLBIST
      implementation options that result in test sequences of different lengths.
      Resistive bridging faults are used as a surrogate of non-target defects.
      Experimental data obtained for largest ISCAS benchmarks suggests that, although
      DLBIST always guarantees complete stuck-at coverage, test sequence length does
      influence the non-target defect detection capabilities. For circuits with a
      large fraction of random-pattern resistant faults, the embedded deterministic
      patterns as well as a sufficient amount of random patterns are both
      demonstrated to be essential for non-target defect detection. It turns out,
      moreover, that area cost is lower for DLBIST solutions with longer test
      sequences, due to additional degrees of freedom for the embedding procedure and
      a lower number of faults undetected by pseudorandom patterns. This implies that
      DLBIST is particularly effective in covering non-target defects.},
   url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2005-116&engl=1}
}

@inproceedings {INPROC-2005-115,
   author = {Hans-Joachim Wunderlich},
   title = {{From Embedded Test to Embedded Diagnosis}},
   booktitle = {Proceedings of the 10th IEEE European Test Sypmposium (ETS'05); Tallinn, Estonia; May 22-25, 2005},
   editor = {IEEE Computer Society},
   address = {Los Alamitos, California},
   publisher = {IEEE Computer Society Conference Publishing Services},
   institution = {University of Stuttgart, Faculty of Computer Science, Electrical Engineering, and Information Technology, Germany},
   series = {IEEE Computer Society Order Number},
   volume = {P2341},
   pages = {216--221},
   type = {Conference Paper},
   month = {May},
   year = {2005},
   isbn = {0-7695-2341-2},
   issn = {1530-1877},
   doi = {10.1109/ETS.2005.26},
   language = {English},
   cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
   department = {University of Stuttgart, Institute of Technical Computer Science, Computer Architecture},
   abstract = {Testing integrated circuits with millions of transistors puts strong
      requirements on test volume, test application time, test speed, and test
      resolution. To overcome these challenges, it is widely accepted to partition
      test resources between the automatic test equipment (ATE) and the circuit under
      test (CUT). These strategies may reach from simple test data
      compression/decompression schemes to implementing a complete built-in
      self-test. Very often these schemes come with reduced diagnostic resolution. In
      this paper, an overview is given on techniques for embedding test into a
      circuit while still keeping diagnostic capabilities. Built-in diagnosis
      techniques may be used after manufacturing, for chip characterization and field
      return analysis, and even for rapid prototyping.},
   url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2005-115&engl=1}
}

@inproceedings {INPROC-2005-114,
   author = {Kiatisevi Pattara and Luis Azuara and Rainer Dorsch and Hans-Joachim Wunderlich},
   title = {{Development of an Audio Player as System-on-a-Chip using an Open Source Platform}},
   booktitle = {Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Kobe, Japan, Vol. 3, May 23-26, 2005},
   publisher = {Institute of Electrical and Electronics Engineers, Inc.},
   institution = {University of Stuttgart, Faculty of Computer Science, Electrical Engineering, and Information Technology, Germany},
   pages = {2935--2938},
   type = {Conference Paper},
   month = {May},
   year = {2005},
   isbn = {0-7803-8834-8},
   doi = {10.1109/ISCAS.2005.1465242},
   language = {English},
   cr-category = {B.0 Hardware General,
                   D.0 Software General},
   department = {University of Stuttgart, Institute of Technical Computer Science, Computer Architecture},
   abstract = {Open source software are becoming more widely-used, notably in the server and
      desktop applications. For embedded systems development, usage of open source
      software can also reduce development and licensing costs. We report on our
      experience in developing a Systemon- a-Chip (SoC) audio player using various
      open source components in both hardware and software parts as well as in the
      development process. The Ogg Vorbis audio decoder targeted for limited
      computing resource and low power consumption devices was developed on the free
      LEON SoC platform, which features SPARC-V8 architecture compatible processor
      and AMBA bus. The decoder runs on the open source RTEMS operating system making
      use of the royalty-free open source Vorbis library. We also aim to illustrate
      the use of hardware/software co-design techniques. Therefore, in order to speed
      up the decoding process, after an analysis, a computing-intensive part of the
      decoding algorithm was selected and designed as an AMBA compatible hardware
      core. The demonstration prototype was built on the XESS XSV-800 prototyping
      board using GNU/Linux workstations as development workstations. This project
      shows that development of SoC using open source platform is viable and might be
      the preferred choice in the future.},
   url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2005-114&engl=1}
}

@inproceedings {INPROC-2005-113,
   author = {Oliver H{\'e}ron and Talal Arnaout and Hans-Joachim Wunderlich},
   title = {{On the Reliability Evaluation of SRAM-based FPGA Designs}},
   booktitle = {Proceedings of the 15th IEEE International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005},
   editor = {IEEE Computer Society},
   publisher = {IEEE Xplore},
   institution = {University of Stuttgart, Faculty of Computer Science, Electrical Engineering, and Information Technology, Germany},
   series = {IEEE Catalog Number},
   volume = {05EX1155},
   pages = {403--408},
   type = {Conference Paper},
   month = {August},
   year = {2005},
   isbn = {0-7803-9362-7},
   doi = {10.1109/FPL.2005.1515755},
   language = {English},
   cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
   department = {University of Stuttgart, Institute of Technical Computer Science, Computer Architecture},
   abstract = {Benefits of Field Programmable Gate Arrays (FPGAs) have lead to a spectrum of
      use ranging from consumer products to astronautics. This diversity necessitates
      the need to evaluate the reliability of the FPGA, because of their high
      susceptibility to soft errors, which are due to the high density of embedded
      SRAM cells. Reliability evaluation is an important step in designing highly
      reliable systems, which results in a strong competitive advantage in today's
      marketplace. This paper proposes a mathematical model able to evaluate and
      therefore help to improve the reliability of SRAM-based FPGAs.},
   url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2005-113&engl=1}
}