@inproceedings {INPROC-2006-80,
   author = {Talal Arnaout and Guenter Bartsch and Hans-Joachim Wunderlich},
   title = {{Some Common Aspects of Design Validation, Debug and Diagnosis}},
   booktitle = {Proceedings of the 3rd IEEE International Workshop on Electronic Design, Test and Applications (DELTA'06); Kuala Lumpur, Malaysia; January 17-19, 2006},
   editor = {IEEE Computer Society},
   address = {Los Alamitos, California},
   publisher = {IEEE Computer Society Conference Publishing Services},
   institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
   series = {IEEE Computer Society Order Number},
   volume = {P2500},
   pages = {3--8},
   type = {Workshop-Beitrag},
   month = {Januar},
   year = {2006},
   isbn = {0-7695-2500-8},
   doi = {10.1109/DELTA.2006.79},
   language = {Englisch},
   cr-category = {B.8 Performance and Reliability},
   department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
   abstract = {Design, Verification and Test of integrated circuits with millions of gates put
      strong requirements on design time, test volume, test application time, test
      speed and diagnostic resolution. In this paper, an overview is given on the
      common aspects of these tasks and how they interact. Diagnosis techniques may
      be used after manufacturing, for chip characterization and field return
      analysis, and even for rapid prototyping.},
   url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2006-80&engl=0}
}

@inproceedings {INPROC-2006-79,
   author = {Jun Zhou and Hans-Joachim Wunderlich},
   title = {{Software-Based Self-Test of Processors under Power Constraints}},
   booktitle = {Proceedings of the 9th Conference on Design, Automation and Test in Europe (DATE'06); Munich, Germany; March 06 - 10, 2006},
   editor = {European Design and Automation Association},
   publisher = {IEEE Xplore},
   institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
   pages = {430--436},
   type = {Konferenz-Beitrag},
   month = {M{\"a}rz},
   year = {2006},
   isbn = {3-9810801-0-6},
   doi = {10.1109/DATE.2006.243798},
   keywords = {test program generation; processor test; low power test},
   language = {Englisch},
   cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
   ee = {http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=1656919},
   department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
   abstract = {Software-based self-test (SBST) of processors offers many benefits, such as
      dispense with expensive test equipments, test execution during maintenance and
      in the field or initialization tests for the whole system. In this paper, for
      the first time a structural SBST methodology is proposed which optimizes
      energy, average power consumption, test length and fault coverage at the same
      time.},
   url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2006-79&engl=0}
}

@inproceedings {INPROC-2006-78,
   author = {Valentin Gherman and Hans-Joachim Wunderlich and Juergen Schloeffel and Michael Garbers},
   title = {{Deterministic Logic BIST for Transition Fault Testing}},
   booktitle = {Proceedings of the European Test Symposium (ETS'06); Southampton, UK; May 22 - 25, 2006},
   editor = {IEEE Computer Society},
   address = {Los Alamitos, California},
   publisher = {IEEE Computer Society Conference Publishing Services},
   institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
   series = {IEEE Computer Society Order Number},
   volume = {P2566},
   pages = {123--128},
   type = {Konferenz-Beitrag},
   month = {Mai},
   year = {2006},
   isbn = {0-7695-2566-0},
   issn = {1530-1877},
   doi = {10.1109/ETS.2006.12},
   keywords = {deterministic logic BIST; delay test},
   language = {Englisch},
   cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
   department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
   abstract = {BIST is an attractive approach to detect delay faults due to its inherent
      support for at-speed test. Deterministic logic BIST (DLBIST) is a technique
      which was successfully applied to stuck-at fault testing. As delay faults have
      lower random pattern testability than stuck-at faults, the need for DLBIST
      schemes is increased. Nevertheless, an extension to delay fault testing is not
      trivial, since this necessitates the application of pattern pairs.
      Consequently, delay fault testing is expected to require a larger mapping
      effort and logic overhead than stuck-at fault testing. In this paper, we
      consider the so-called transition fault model, which is widely used for
      complexity reasons. We present an extension of a DLBIST scheme for transition
      fault testing. Functional justification is used to generate the required
      pattern pairs. The efficiency of the extended scheme is investigated by using
      industrial benchmark circuits.},
   url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2006-78&engl=0}
}

@inproceedings {INPROC-2006-77,
   author = {Nabil Badereddine and Patrick Girard and Serge Pravossoudovitch and Christian Landrault and Arnaud Virazel and Hans-Joachim Wunderlich},
   title = {{Minimizing Peak Power Consumption during Scan Testing: Test Pattern Modification with X Filling Heuristics}},
   booktitle = {Proceedings of the Conference on Design \& Test of Integrated Systems in Nanoscale Technology (DTIS), Tunis, Tunisia, September 5 - 7, 2006},
   publisher = {Institute of Electrical and Electronics Engineers},
   institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
   pages = {359--364},
   type = {Konferenz-Beitrag},
   month = {September},
   year = {2006},
   isbn = {0-7803-9727-4},
   doi = {10.1109/DTIS.2006.1708693},
   keywords = {Dft; scan testing; power-aware testing; peak power consumption},
   language = {Englisch},
   cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
   department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
   abstract = {Scan architectures, though widely used in modern designs, are expensive in
      power consumption. In this paper, we discuss the issues of excessive peak power
      consumption during scan testing. We show that taking care of high current
      levels during the test cycle (i.e. between launch and capture) is highly
      relevant to avoid noise phenomena such as IR-drop or ground bounce. We propose
      a solution based on power-aware assignment of donīt care bits in deterministic
      test patterns. For ISCASī89 and ITCī99 benchmark circuits, this approach
      reduces peak power during the test cycle up to 89\% compared to a random filling
      solution.},
   url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2006-77&engl=0}
}

@inproceedings {INPROC-2006-76,
   author = {Nabil Badereddine and Patrick Girard and Serge Pravossoudovitch and Christian Landrault and Virazel Arnaud and Hans-Joachim Wunderlich},
   title = {{Structural-based Power-aware Assignment of Don't Cares for Peak Power Reduction during Scan Testing}},
   booktitle = {Proceedings of the IFIP International Conference on Very Large Scale Integration (vlsi-soc), Nice, France, October 16 - 18},
   publisher = {International Federation for Information Processing},
   institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
   pages = {403--408},
   type = {Konferenz-Beitrag},
   month = {Oktober},
   year = {2006},
   isbn = {3-901882-19-7},
   doi = {10.1109/VLSISOC.2006.313222},
   language = {Englisch},
   cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
   department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
   abstract = {Scan architectures, though widely used in modern designs for testing purpose,
      are expensive in power consumption. In this paper, we first discuss the issues
      of excessive peak power consumption during scan testing. We next show that
      taking care of high current levels during the test cycle (i.e. between launch
      and capture) is highly relevant so as to avoid noise phenomena such as irdrop
      or ground bounce. Then, we propose a solution based on power-aware assignment
      of donīt care bits in deterministic test patterns that considers structural
      information of the circuit under test. Experiments have been performed on
      ISCASī89 and ITCī99 benchmark circuits with the proposed structural-based
      power-aware X-Filling technique. These results show that the proposed technique
      provides the best tradeoff between peak power reduction and increase of test
      sequence length.},
   url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2006-76&engl=0}
}

@inproceedings {INPROC-2006-75,
   author = {Christian Zoellin and Hans-Joachim Wunderlich and Nicolas Maeding and Jens Leenstra},
   title = {{BIST Power Reduction Using Scan-Chain Disable in the Cell Processor}},
   booktitle = {Proceedings of the International Test Conference (ITC); Santa Clara, CA, USA; October 24 - 26, 2006},
   editor = {International Test Conference},
   address = {Washington, D.C.},
   publisher = {IEEE Xplore},
   institution = {Universit{\"a}t Stuttgart, Fakult{\"a}t Informatik, Elektrotechnik und Informationstechnik, Germany},
   series = {IEEE Catalog Number},
   volume = {06CH37787},
   pages = {1--8},
   type = {Konferenz-Beitrag},
   month = {Oktober},
   year = {2006},
   isbn = {1-4244-0292-1},
   issn = {1089-3539},
   doi = {10.1109/TEST.2006.297695},
   keywords = {microprocessor test; BIST; low power test.},
   language = {Englisch},
   cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
   department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
   abstract = {Built-in self test is a major part of the manufacturing test procedure for the
      Cell Processor. However, pseudo random patterns cause a high switching activity
      which is not effectively reduced by standard low power design techniques. If
      special care is not taken, the scan-speed may have to be reduced significantly,
      thus extending test time and costs. In this paper, we describe a test power
      reduction method for logic BIST which uses test scheduling, planning and
      scan-gating. In LBIST, effective patterns that detect additional faults are
      very scarce after a few dozens of scan cycles and often less than one pattern
      in a hundred detects new faults. In most cases, such an effective pattern
      requires only a reduced set of the available scan chains to detect the fault
      and all donīt-care scan chains can be disabled, therefore significantly
      reducing test power.},
   url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=INPROC-2006-75&engl=0}
}

@article {ART-2006-15,
   author = {Yuyi Tang and Hans-Joachim Wunderlich and Piet Engelke and Ilian Polian and Bernd Becker and Juergen Schloeffel and Friedrich Hapke and Michael Wittke},
   title = {{X-Masking During Logic BIST and its Impact on Defect Coverage}},
   journal = {IEEE Transactions on Very Large Scale Integrated (VLSI) Systems},
   publisher = {The Institute of Electrical and Electronics Engineers, Inc.},
   volume = {14},
   number = {2},
   pages = {193--202},
   type = {Artikel in Zeitschrift},
   month = {Februar},
   year = {2006},
   issn = {1063-8210},
   doi = {10.1109/TVLSI.2005.863742},
   keywords = {Defect coverage; logic built-in self test (BIST); resistive bridging faults (RBFs); X-masking},
   language = {Englisch},
   cr-category = {B.8.1 Reliability, Testing, and Fault-Tolerance},
   department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
   abstract = {We present a technique for making a circuit ready for logic built-in self test
      by masking unknown values at its outputs. In order to keep the silicon area
      costs low, some known bits in output responses are also allowed to me masked.
      These bits are selected based on a stuck-at n-detection based metric, such that
      the impact of masking on the defect coverage is minimal. An analysis based on a
      probabilistic model for resistive short defects indicates that the coverage
      loss for unmodeled defects is negligible for relatively low values of n.},
   url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-2006-15&engl=0}
}

@article {ART-2006-14,
   author = {Bernd Becker and Ilia Polian and Sybille Hellebrand and Bernd Straube and Hans-Joachim Wunderlich},
   title = {{DFG-Projekt RealTest - Test und Zuverl{\"a}ssigkeit nanoelektronischer Systeme}},
   journal = {it - Information Technology},
   publisher = {Oldenbourg Wissenschaftsverlag},
   volume = {48},
   number = {5},
   pages = {304--311},
   type = {Artikel in Zeitschrift},
   month = {Oktober},
   year = {2006},
   issn = {1611-2776},
   doi = {10.1524/itit.2006.48.5.304},
   keywords = {Nanoelektronik; Entwurf; Test; Zuverl{\"a}ssigkeit; Fehlertoleranz/Nano-electronics; Design; Test; Dependability; Fault Tolerance},
   language = {Deutsch},
   cr-category = {B.7 Integrated Circuits},
   department = {Universit{\"a}t Stuttgart, Institut f{\"u}r Technische Informatik, Rechnerarchitektur},
   abstract = {Entwurf, Verifikation und Test zuverl{\"a}ssiger nanoelektronischer Systeme
      erfordern grundlegend neue Methoden und Ans{\"a}tze. Ein robuster Entwurf wird
      unabdingbar um Fertigungsfehler, Parameterschwankungen, zeitabh{\"a}ngige
      Materialver{\"a}nderungen und vor{\"u}bergehende St{\"o}rungen zu tolerieren. Gleichzeitig
      verlieren gerade dadurch viele traditionelle Testverfahren ihre Aussagekraft.
      Im Rahmen des Projekts RealTest werden einheitliche Entwurfs- und
      Teststrategien entwickelt, die sowohl einen robusten Entwurf als auch eine
      darauf abgestimmte Qualit{\"a}tssicherung unterst{\"u}tzen.},
   url = {http://www2.informatik.uni-stuttgart.de/cgi-bin/NCSTRL/NCSTRL_view.pl?id=ART-2006-14&engl=0}
}